1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device using a photolithography technique and, more particularly, to a method of manufacturing a semiconductor device using a measurement mark pattern.
2. Description of the Related Art
In the manufacturing process of a semiconductor device, various pattern films, opening portions, and the like are formed using a photolithography technique. When a pattern or opening portion is to be formed in an upper layer, the pattern or opening portion must be relatively aligned with the pattern of a lower layer. For example, in formation of a contact for electrically connecting the upper and lower wiring layers with each other, if this contact is misaligned, the contact is formed in the wiring layer or layers. In formation of the source/drain of a MOS transistor, if a mask film as an upper layer is misaligned, an impurity may be injected in a region, deviated from an expected region, of a lower layer, resulting in a defective device.
In addition, the electrical characteristics of a MOS transistor or other devices of this type, e.g., various specifications such as an operation speed, a capacitance, and a threshold voltage are often determined by the two-dimensional size of a structure formed on a semiconductor substrate. If a size error is caused due to the above-described misalignment or upon exposure, desired characteristics cannot be obtained in some cases. Therefore, size measurement need to be performed in formation of each pattern.
Conventionally, alignment marks are formed on lower and upper layers. A superposition error between these alignment marks is measured, thereby performing the above-described alignment. As for a to-be-formed layer, a size measurement mark is formed, and after exposure, the size of the developed size measurement mark is measured, thereby detecting a size error.
In this case, in the former measurement of an alignment error, alignment marks each having a size of about several .mu.m or more are formed. Each alignment mark is visually read by using a microscope, and a misalignment between the alignment marks of the upper and lower layers is measured, thereby measuring an alignment error. Alternatively, the alignment mark is detected using an optical system. The obtained image is converted into an electrical signal, and a predetermined process is performed, thereby measuring an alignment error.
In the latter measurement of a size error, a size measurement mark having almost the same size (1 .mu.m or less) as that of the element pattern of a device is formed. An electron beam is scanned on the measurement mark, and secondary electrons emitted thereupon are detected. A size is calculated in accordance with the intensity waveform of the secondary electrons.
For this reason, in the conventional manufacturing process, measurement of an alignment error and measurement of a size error must be performed by different apparatuses, and it is difficult to simultaneously perform these measurements. In addition, since the processing method for detecting the alignment marks is different from that for the size measurement mark, and precisions required for the two detection processes are largely different, it is not preferable to perform these measurements using the same mark. For example, if an alignment mark having a size of several .mu.m is used for measurement of a size, a very small size error cannot be measured. To the contrary, if a size measurement mark having a size of 1 .mu.m or less is used for measurement of an alignment error, size and alignment errors of such a small mark cannot be measured because of the limited precision of the apparatus. As described above, it is conventionally difficult to simultaneously perform measurement of a size error and measurement of an alignment error. As a result, these measurements must be independently performed.
Therefore, in the conventional photolithography process, as shown in the flow chart of FIG. 1, test exposure (pilot exposure) is performed for one or several semiconductor substrates. Alignment between an alignment mark of a lower layer and an alignment mark of an upper layer is determined by an operator or using an apparatus, and an alignment error is measured and fed back. Thereafter, all the remaining semiconductor substrates are exposed. A size error is measured for each exposed substrate using a size measurement mark after development of a photoresist. If any substrate is determined to fall outside a specified range, the photoresist process from coating is repeated. As for a substrate falling inside the specified range, an alignment error is measured again. If the substrate is determined to fall outside the specified range, the photoresist process from coating is performed again.
For this reason, conventionally, some substrates having size errors within a specified range may be determined as defective upon measurement of an alignment error, so the manufacturing efficiency of semiconductor devices becomes low. To the contrary, when measurement of a size error is performed after measurement of an alignment error, some substrates having alignment errors within a specified range are determined as defective upon measurement of the size error. This also results in a low manufacturing efficiency of semiconductor devices.